This invention relates to a method and system for writing data to a memory or storage device that stores multiple bits per cell, and particularly to a method and system for reducing latency in writing data to such a storage device.
As discussed in more detail below, flash memory cells (in particular, floating gate flash memory cells) store data by changing the number of electrons trapped on the floating gate. A memory cell may be programmed by inserting electrons onto the floating gate (e.g., via channel hot-electron programming or Fowler-Nordheim tunneling), and a memory cell may be erased by extracting electrons from the floating gate. Programming a cell corresponds to moving the cell from a lower state (e.g., an erase state) to a higher state. Programming can be addressed to individual flash cells within an array of cells, while erasing typically can be performed only on all cells in an array of memory cells. Thus, during flash programming, only state transitions from a lower state to a higher state are permitted. Transitions in the other direction are not permitted, because moving to a lower state would mean erasing not only the cell being programmed, but all cells in the array.
When a flash device is being used as multilevel cell (MLC) flash memory to store multiple bits per cell, the physics of the device, as described above, may limit the state transitions that are permitted without completely erasing the cell and therefore the array. In known methods for programming such memory cells, whenever data are received that require changing the value of a bit position, the memory state of the cell is changed in such a way that all other bit positions retain their previous values. However, in such techniques, depending on the order in which bits arrive, this may require an invalid state transition for programming of a subsequent bit position, causing an error condition or failure.
Alternatively, the cell may not be rewritten until data for all bit positions to be programmed arrive, so that the final state is known before any writing occurs. The resulting latency may be particularly acute if the different bits, as is frequently the case, belong to different logical data pages. According to another alternative, the encoded states may be mapped to a different set of states that do not result in invalid state transitions, but this also requires waiting for all memory pages to arrive, causing latency.